array bit parameter range in verilog - underflow or -1

Question

What should be index ranges of parameter init in this case:

parameter zero = 0;

parameter bit[31:0] size = 32'b01;

parameter bit[((zero * size) - 1):0] init = 2'b11;

It should be [-1:0] or [4294967295:0] and why? Is such behavior standardized or it depends on tool?

Answer 1

According to the LRM, the range in an array declarations are signed integer expressions. It should cast the 32-bit unsigned expression to a signed integer. So the result is -1. You can test this by displaying the result of $left(init)

Whether all tool developers have read the LRM is another question.