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verilogsystem-verilogmodelsimintel-fpga

Shifter output is always 0 when using concatenation and case

I have the following code:

module shifter(
    input[7:0] in,
    input[1:0] amt,
    output logic[7:0] out
);

always_comb case(amt)
    2'h0: out = in;
    2'h1: out = {{in[6:0]}, 0};
    2'h2: out = {{in[5:0]}, 0, 0};
    2'h3: out = {{in[4:0]}, 0, 0, 0};
    default: out = in;
endcase

endmodule

It describes a simple shifter which takes in the amount of shifts through the amt input. The problem is that no matter what the value of amt is (except 0), out is always 0 as seen on this waveform from a test:

enter image description here

Am I concatenating wrong? Examples I've seen online are similar to this, however.

Solution

  • Try constraining the size of the 0 to 1'b0 in 2'h1: out = {{in[6:0]}, 0};. What happens is that you are assigning a concatenation of in[6:0] and 32-bit (default width) 0, so only LSBs of the 0 goes to the out.

    Also, default is redundant since you've described all the possible cases for amt.