We are planning to develop a stand-alone board with one Xilinx FPGA that needs to communicate with several onboard modules. Some of these modules have a PCIe interface and thus working as a PCIe Endpoint. We don't have many experience in this field but what we have managed to know so far is that we need to use the PCIe IP Core inside the FPGA, working as a Root Port, to comunicate whith these chips. As I understand we also need to use a PCIe switch between the FPGA and the endpoints to expand the PCIe bus. To manage all the communication between these devices we are thinking implementing a MicroBlaze CPU Soft Core and PetaLinux.
My questions are:
Who is the responsable to do the PCIe endpoints enumeration, the PetaLinux OS or the Root Port IP Core?
With the PCIe switch in the middle, do I need some kind of driver for it to work or it is full transparent and the OS or Root port just see all the PCIe endpoints connected to the downstream port?
The operating system, drivers and socalled PCIe subsystem behind the PCIe root complex does the enumeration.
As the name "switch" says, it's transparent. Nonetheless, some switches have extra functionality to program link counts, lane counts, QoS, hot-failover, ...
The PCIe switch get's also configured while enumeration by the PCIe subsystem driver.
This book might help: PCI Express Technology 3.0 from Mindshare Press.