Forcing multiple wires in design in SV/UVM

Question

I'm new to System Verilog and UVM, and I've already seen this thread:

Regex in SV or UVM

I can't find anywhere a proper example on what kind of syntax should I use to force multiple wires in a design, using regular expressions/wildcards.

For example:

Let's say I have a module called my_fifo, which Is instanced in the design multiple times:

top.dut.my_fifo_in
top.dut.master.my_fifo_a
top.dut.slave.axi.my_fifo_out

And the block my_fifo contains a wire called:

wire force_me_to_1 = 1'b0;

I want to force that wire in all instances that start with "my_fifo". Something like (excuse me for the syntax, it's only for clarifying my intentions):

force "*my_fifo*.force_me_to_1" = 1'b1;

And it'll make that wire to 1 in all above instances.

Answer 1

There is no direct way to do what you want, however there are some tricks which you might be able to explore in your case.

Supposedly that somewhere in a top instance you define a flag, say force_me

module tb_top;
    bit force_me = 0;
    ...
endmodule

in your module you can write something like the flowing:

module my_fifo;

    logic force_me_to_1;

    always @(tb_top.force_me) begin
        if (tb_top.force_me)
            force force_me_to_1 = 1;
        else
            release force_me_to_1;
    end
    ..
 endmodule

now in your testbench you should be able to say

 tb_top.force_me = 1;
 ...
 tb_top.force_me = 0;

This should force the signal in all instances of the module 'my_fifo' (from inside the module :-))