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What is the purpose of UVM Virtual Sequencers

I am trying to figure out what the purpose of a UVM Virtual Sequencer is.

If you look at what verification academy says about it. It is basically a container class for other sequencers.

class sequencer extends uvm_virtual_sequencer;

`uvm_component_utils(virtual_sequencer)

 sequencer_a m_seq_a;
 sequencer_b m_seq_b;
...
...
endclass

One just does a heretical reference to m_seq_a or m_seq_b when doing a start on their sequence.

Why isn't a virtual sequencer just a uvm_component? Is there something that a uvm_virtual_sequencer can do? One can't do a start on the virtual sequencer.

Solution

  • There are 2 ways to start virtual sequences (which will in turn start different sequences on different sequencers).

    • Keep the handles of the target sequencers in the virtual sequences and then assign those handles before starting the sequence.

    Like this.

    vir_seq vira = vir_seq::type_id::create("virtual_sequence");

vira.sequencer_1 = .... ; // sequencer 1 hierarchical path
vira.sequencer_2 = .... ; // sequencer 2 hierarchical path

vira.start(null); // Start the virtual sequence using null
    • Keep the handles of the target sequencers in another sequencer (virtual sequencer) and start the virtual sequence on that virtual sequencer.

    However the approach of Virtual Sequencer is not recommended, as it just adds another layer of hierarchy and is complicated for reuse.

    Another point is that, uvm_virtual_sequencer is nothing but a uvm_sequencer only, and it can't be a uvm_component, as the virtual sequence will be started on it.

    Here is the relevant code from the UVM 1.2 source code.

    typedef uvm_sequencer #(uvm_sequence_item) uvm_virtual_sequencer