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Can there be two 'uvm_tlm_b_target_socket' and two corresponding 'b_transport' implementation in a single object?

I have a requirement where I need to have two uvm_tlm_b_target_socket in class as it going to receive a transaction from two different agents. I need to process the data received from the two sockets differently so I cannot have a single implementation of b_transport task. Is there anything equivalent for target socket to terminator of analysis ports were we can use uvm_analysis_imp_decl macro which allows us to have a different implementation of write function? In the class reference manual I could find this macro uvm_blocking_transport_imp_decl but couldn't find an example of how to use this. In summary I am trying to do this

uvm_tlm_b_target_socket A;
umv_tlm_b_target_socket B;

// b_transport task implementation for socket "A"
task b_transport;

// b_transport task implementation for socket "B"
task b_transport;
Solution

  • Aside from the classical TLM2 sockets, there are also *_transport_imps. As far as I could tell, these do the same thing as sockets. You use the *_decl macro just like you use uvm_analysis_imp_decl:

    class some_class;
  `uvm_blocking_transport_imp_decl(_a)
  `uvm_blocking_transport_imp_decl(_b)

  uvm_transport_imp_a A;
  umv_transport_imp_b B;

  task b_transport_a(...);
  task b_transport_b(...);
endclass