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verilogtest-bench

testbench: how to load a known sequence of bits on 1bit data input

-In my Verilog test bench i would like to continuously load a known sequence of bits to the da+ input port (size 1bit) and change following the posedge or negedge edge of clock DCO+. -This is the sequence that i would like to load on DA+ : 1010 0000 0111 1111 -Please have a look to the screenshot attached for more clarification1

Have you any idea to make it in Verilog testbench?

please note that i use ISE14.7 and Isim as similator Thank you.

Best Regards

relation betwween da+ and DCO+

Solution

  • Since the load value is constant, you can store it in an array and keep loading it to DA at every posedge or negedge of DCO.You would also need to generate the clock DCO and then instantiate the design. 

    reg DCO;
reg DA;
reg [15:0] DA_array = 16'hA07F;
integer i;

initial begin
   for(i=0;i<16;i=i+1)
     @(DCO) DA <= DA_array[i];
end