Testing workflow for small (i.e. one person) design in SystemVerilog

Question

I started implementing design in SystemVerilog but I'm a bit lost as far as testing is concerned. I tried to use straightforward SystemVerilog for verification but it seems limited:

• The errors are spotted by going through the log (even $error and assert don't stop simulation) so they can be easily missed.
• I cannot (?) run all the tests as Vivado allows to use only one as active
• I could put everything in single test simulation but waveform for debugging seems too long as it mixes various tests.
• I can try to create my own framework but it sounds like reinventing the wheel which is bad idea.

I know of SVUnit but it seems to work with expensive simulators, not xsim I have license for. I'm trying to look at UVM but I'm not sure if the investment of time is worth it.

What would be a good test workflow for SV for person coming from software (drivers) for personal, one-person, FPGA project?

Answer 1

Running all tests isn't usually done in one simulator invocation. This is handled as multiple invocations by a different tool, which usually does more (distribute jobs across a compute farm, centralizes status, etc.).

Determining whether a test passed or failed is usually done by inspecting the log file. If an error was detected, it should show up in the log and you can grep for it. The simulator's exit code isn't used for this, since non-zero exit codes mean that something was wrong with the tool invocation, not with the simulation itself.

In your case, since you only have the simulator available you have to build a lot of the infrastructure. You'll need a script that can run a single test and can determine if it was a PASS or a FAIL (via grep, Perl, etc.). You can then define another script that loops over all of your tests, calls the previous script and computes a summary.