If there are 2 always blocks which block will be executed first

I am new to verilog and I have a question

Suppose I have 2 always blocks in a module, which block will be executed first or will they be executed at the exact same time. If so what is the value of r1. For example

module example(clk);
input clk;
reg r1;
always @ (posedge clk)
  r1 <= 1'b0;
always @ (posedge clk)
  r1 <= 1'b1;
endmodule

TIA

Solution

The two always blocks create two processes that execute in parallel. Both processes will block waiting for a rising clk event. When that event happens, both processes will schedule to resume. However, Verilog/SystemVerilog simulators use an event queue that serializes everything that is supposed to happen simultaneously. There's no way for you to predict which process gets scheduled first; it is a simulation race condition. In practice, one particular version of a simulator will always choose one process before another, so you will always see the same result. But that result might change if you switch to a different tool, or even change some options in the tool for debugging or optimization.