Search code examples
verilogsystem-veriloghdl

I'm getting error when I use conditional operation


I've written a line using a conditional operator as shown below:

assign {RS2, RS1} = (!DisM || !DisX)? (RdEn==2'b00? (!DisI? {rs2, rs1} : 64'bz) : (RdEn==2'b01? (!switch? {rs2, Rn} : {Rn, rs1}) : {Rm, Rn}))) : 64'bz;
  1. RS2 & RS1 are 32 bit output wires.
  2. Rn & Rm are 32 bit inputs.
  3. rs1 & rs2 are 32 bit registers.
  4. RdEn is 2bit register.
  5. DisI and switch are one bit register.

enter image description here

The simulator (Icarus 0.9.7 or any) is showing there is a syntax error in the above line.

Here is my code which addresses the same problem:

module TEST(Rn, Rm, DisM, DisX, DisI, switch, RdEn, RS1, RS2);
input [31:0]Rn, Rm;
input DisM, DisX, DisI, switch;
input [1:0]RdEn;
output [31:0]RS1, RS2;

reg [31:0]rs1, rs2;

always@*
begin
    rs1 = Rn + 32'd7;
    rs2 = Rm - 32'd7;
end

assign {RS2, RS1} = (!DisM || !DisX)? (RdEn==2'b00? (!DisI? {rs2, rs1} : {64{1'bz}}) : (RdEn==2'b01? (!switch? {rs2, Rn} : {Rn, rs1}) : {Rm, Rn}))) : {64{1'bz}};

endmodule

Solution

  • The compiler interpreted the ? in RdEn==2'b00? as a 3rd bit instead of as the ternary operator. Just add a space between b00 and ?. Same for b01?.

    ? is a valid z_digit. Refer to IEEE Std 1800-2012, section 5.7 Numbers.

    Also, you had a mismatched number of parentheses (a good editor can show this):

    assign {RS2, RS1} = (!DisM || !DisX)? (RdEn==2'b00 ? (!DisI? {rs2, rs1} : {64{1'bz}}) : (RdEn==2'b01 ? (!switch? {rs2, Rn} : {Rn, rs1}) : {Rm, Rn})) : {64{1'bz}};
    

    It is also good practice to use {64{1'bz}} to make sure you get 64 bits of 1'bz.