verilog, why is this illegal reference to net

Question

i am new to verilog but i don't get why is this illegal reference to net for signal (subcounter_of_counter). I mean it's combinational logic

thanks in advance :)

wire [n-1:0] subcounter_of_counter;
reg [n-1:0] mask,free;     
always @(*) begin //command or id or mask or free or subcounter_of_counter
        if (command==increment) begin
            for (int i = 0; i < n; i=i+1)begin
                if (i<id) begin
                    subcounter_of_counter[i]=1'b0;
                end else if (i==id) begin
                    subcounter_of_counter[i]=1'b1;
                end else begin
                    if( (|mask[id+1:i]) || (|free[id+1:i]) ) begin
                        subcounter_of_counter[i]=1'b0;
                    end else begin
                        subcounter_of_counter[i]=1'b1;
                    end
                end
            end
        end
        end

Answer 1

A wire is a nettype, and a nettype cannot be assigned in an always blocks or initial blocks.
Change subcounter_of_counter from wire to reg to resolve your issue. reg is an keyword for a logic type and does not explicitly mean it will synthesize to a register.