VHDL Why is state S0 active when it isn't supposed to be?

Question

I'm having some trouble with this piece of code. It seems that state S0 is always active, even when it is not supposed to be. It appears that the output of this state is inverted(active when it is supposed to be disabled). Any ideas? Print of the simulation at the bottom. Thanks

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ControlUnit is
     port(clk           : in  std_logic;
          reset         : in  std_logic;
          validTime     : in  std_logic;
          timeData      : in  std_logic_vector(3 downto 0);
          writeEnable   : out std_logic;
          writeAddress  : out std_logic_vector(3 downto 0);
          averageReady  : out std_logic);
end ControlUnit;

architecture Behavioral of ControlUnit is
    type TState is (S0, S1, S2, S3, S4, S5);
    signal PState, NState: TState;
begin

    sync_proc: process(clk, reset)
    begin
        if(reset = '1') then
            PState <= S0;
        elsif(rising_edge(clk)) then
            PState <= NState;
        end if;
    end process;

    comb_proc: process(PState, validTime, timeData)
    begin
        averageReady <= '0';
        writeEnable <= '0';
        case PState is
            when S0 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S1;
                else
                    NState <= S0;
                end if;
            when S1 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S2;
                else
                    NState <= S1;
                end if;
            when S2 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S3;
                else
                    NState <= S2;
                end if;
            when S3 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S4;
                else
                    NState <= S3;
                end if;
            when S4 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S5;
                else
                    NState <= S4;
                end if;
            when S5 =>
                averageReady <= '1';
                NState <= S0;
            when others =>
                NState <= S0;
        end case;
    end process;

    with PState select
        writeAddress <= "0000" when S0,
                             "0001" When S1,
                             "0010" when S2,
                             "0011" when S3,
                             "0100" when S4,
                             "XXXX" when others;
end Behavioral;

Here's a print of the simulation:

(clickable)

Answer 1

Everything is ok with your code. Why do you suppose S0 state is always active? You can't say it from waveform, cause you don't know encoding scheme. On the other hand you writeAddress signal changes constantly meaning that your state machine changes its state.