Use a variable for hierarchical path in verilog configuration

Question

I have a UVM testbench that uses configurations to replace a VHDL component that is deep within the design. Each test that I create has to use a verilog configuration to replace that component. Is there a way to use a variable for the hierarchical path so that I don't have to update each configuration if the VHDL design changes?

Answer 1

There is no way to use a variable to represent a hierarchical path, except for virtual interface variables used to represent the hierarchical path to interface instances.

You will need to show use an example of how each test changes the VHDL component to give us a better idea for a solution; maybe you can use a macro.