System Verilog: The loop variable is not initialized to a constant ELAB-800

Question

When trying to compile my RTL design that is written in System Verilog, I am using Synopsys Design Compiler, but I am getting the following error message:

Error: /home/rtl/mydesign.sv:66: The loop variable is not initialized to a constant. (ELAB-800)

Here is the code in question:

// Zero out bits from savedbit_loc all the way down to the least significant bit
// We don't know the value of savedbit_loc until the module is instantiated.

assign savedbit_loc = src1- MYPARAM1 - 1;

// Zero out the 
always @(*) begin
    for (int i = savedbit_loc; i >= 0; i--) begin  
        zeroedout[i] = 1'b0;
  end
end

MYPARAM1 is a parameters that are set when the module is instantiated.

The line it is complaining about is:

for (int i = savedbit_loc; i >= 0; i--) begin

My code runs in ncverilog just fine and obtains the correct output.

Is there another way to write this module so that i don't get this error?

Answer 1

Assuming MYPARAM1 and MYPARAM2 are declared as parameters, then make savedbit_loc a parameter too.

localparam int savedbit_loc = MYPARAM1 - MYPARAM2 - 1;

Also, always use always_comb instead of always @(*)

The big advantage is that always_comb guarantees to execute at a least once time 0, where as always @(*) waits for an event. This can cause differences in simulation if the block only contains constants on the RHS.

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Based on your updated question, what you probably want is

myval = myval & (32'('1) <<savebit_loc);