Sequence name as a task input

Question

I have a SPB register sequence which sets up the hardware register values in a particular configuration. The values of this configuration are used by a subsequent DAI sequence, by assigning the register values to the DAI sequence values. I have managed this correctly using the following code to assign the register values to temporary ints to be used to constraint the DAI Sequence:

 task assign_reg_value();

    `uvm_info ("VIRT_SEQ_MODEL_PRINT", $sformatf ("Initial Register Setup : %s", ljf_reg_wr_seq.model.sprint()), UVM_LOW)



    //------------------------------------------------------------------------------------------------------
    //Get the register field value and assign it to the temporary variable. These are used for the serial 
    //sequence
    //------------------------------------------------------------------------------------------------------
    //DAI_CTRL
    seq_ser_format      = ljf_reg_wr_seq.model.DAI_CTRL.format.get();

    //MORE LINES SIMILAR TO ABOVE HERE 

endtask

However, in the event of running more than one register sequence to have different configurations in a single simulation, I require a method of generalising the above task such that it takes the sequence name argument. Without this, I would need to replicate the ~50 lines of code and change the sequence name. The pseudo code below shows the functionality that I require:

seq_ser_format = <seq_name>.model.DAI_CTRL.format.get(); 

I guess that there is a way to do this by setting the register sequence name in the configuration database before it is run, then retrieving it inside the task after it has finished running. Does anybody have any suggestions for this implementation? Can it be done using the config database?

Answer 1

In your test/virtual sequence, you can implement your task as follows:

task assign_reg_value(my_base_sequence seq);
  // ...
  seq_ser_format = seq.get_format_reg();
endtask

I assume your sequences are extended from base class my_base_sequence. Then you need to implement the above function get_format_reg() in your my_base_sequence as virtual method and override it in your subclasses.

class my_base_sequence extends uvm_sequence;
  // ...
  virtual function int get_format_reg();
     // leave it empty
     $display("Not implemented in base class");
  endfunction
endclass

class ljf_reg_wr_sequence extends my_base_sequence;
// ...
  virtual function int get_format_reg();
    return this.mode1.DAI_CTRL.format.get();
  endfunction
endclass

Then in your test/virtual sequence:

// ...
ljf_reg_wr_sequence ljf_reg_wr_seq;
other_reg_sequence other_seq;
// ... create sequence

assign_reg_value(ljf_reg_wr_seq);
// do something
assign_reg_value(other_seq);
// ...