Error (10170): expecting "<=", or "=", or "+=", or "-=", or "*=", or "/=", or "%=", or "&=", or "|=", or "^=", etc

Question

module accumulator (
    input [7:0] A ,
    input reset,
    input clk,
    output reg carryout,
    output reg overflow,
    output reg [8:0] S,
    output reg HEX0,
    output reg HEX1,
    output reg HEX2,
    output reg HEX3
    );

    reg signA;
    reg signS;
    reg [7:0] magA;
    reg [7:0] magS;
    reg Alarger;

    initial begin
        S = 9'b000000000;
    end

    always_ff @ (posedge clk, posedge reset) begin
        if (reset) begin
            S = 9'b000000000;
        end
        else begin

            begin
            signA <= A[7];              //Is A negative or positive
            signS <= S[7];
            S <= A + S;
            end

            if (signA == 1) begin           //A is negative so magnitude is of 2s compliment
                magA <= (~A[7:0] + 1'b1);
            end
            else begin
                magA <= A;
            end

            if (signS == 1) begin           //sum is negative so magnitude is of 2s compliment
                magS <= (~S[7:0] + 1'b1);
            end
            else begin
                magS <= S;
            end

            if (magA > magS) begin
                Alarger <= 1'b1;        //Magnitude of A is larger than magnitude of sum
            end
            else begin
                Alarger <= 1'b0;
            end

            if ((signA == 1) & (Alarger == 1) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 1) & (Alarger == 0) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 1) & (signA == 1) & (S[7] == 0)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if ((signS == 0) & (signA == 0) & (S[7] == 1)) begin
                overflow <= 1'b1;
            end
            else begin
                overflow <= 1'b0;
            end
            if (S[8] == 1) begin            //carryout occurred
                carryout <= 1'b1;
                overflow <= 1'b0;
                S <= 9'b000000000;      //sum no longer valid
            end
            else begin
                carryout <= 1'b0;
            end

            display_hex h1                  //display of A
            (
                .bin            (magA),
                .hexl           (HEX2),
                .hexh           (HEX3)
            );

            display_hex h2                  //display of sum
            (
                .bin            (S[7:0]),
                .hexl           (HEX0),
                .hexh           (HEX1)
            );
        end
    end

endmodule 

I am trying to make an accumulator that adds A (8 digit binary value that can be signed or unsigned) repeatedly to the sum. Once the sum is computed, then sum and A should display the value on 4 hex display LEDs (2 LEDs for A and 2 LEDs for sum). However, I am having a hard time getting it to compile. I have searched the error code and it seems like a general error for a syntax error and can have several meanings.

Answer 1

I was not able to reproduce the exact error, but moving the instantiations of display_hex outside always_ff resolves the main issue:

module accumulator
(
    /* ... */
);
    // ...

    always_ff @ (posedge clk, posedge reset) begin
        /* ... */
    end

    display_hex h1 (
        /* ... */
    );

    display_hex h2 (
        /* ... */
    );
endmodule

Another thing: The code drives variable S from initial as well as always. This creates multiple drivers and the code will not compile. To fix this, remove the initial completely, you don't need it since S will be set to 0 when reset is asserted.

OR

You can move all the logic into the initial block; it'd look something like this (but this, most probably, won't synthesize):

initial begin
    S = 0;

    forever begin
        wait @(posedge clock);

        // Do stuff here ..
    end
end