I have Xilinx background and now I happened to write some code on Altera devices. I have a question about generating post-synthesis models (also post-fit). On Xilinx I had netget which was able to generate verilog or vhdl post-synthesis model of my design which I was able to use freely for example in iverilog compiler. I quartus ii i have found quartus_eda tool but I am not able to perform what I wanted, I can generate *.vo files which looks fine but I am not able to find libraries to cover elements used there. I am using --tool=modelsim. Where I should look after them ?
See ModelSim-Altera Precompiled Libraries for pre-compiles libraries for Altera devices in ModelSim simulation.
The Preparing for EDA Simulation may also be helpful.
However, you may re-consider doing post-synthesis/fit simulation, since functional simulation at RTL level combined with Static Timing Analysis (STA) maybe an alternative approach. If the intention is to verify timing with post-fit simulation, then note that Altera apparently is abandoning this support for this, since timing information in Standard Delay Format Output File (.sdo) files is not generated for post-fit simulation information for e.g. Cyclone V devices.