VHDL signal not assigned in every case statement

Question

If I have a the following case statement in a VHDL code

case state is
    when ST_STATE1 =>
        a <= '1';
    when ST_STATE2 => 
        b <= '1';
    when ST_STATE3 =>
        a <= '0';
        b <= '0';
end case;

Given that a and b are correctly initialized and defined at reset. I understand that there will be a latch for b in ST_STATE1 and a latch for a in ST_STATE2, but is this something bad? The expected behavior would be the one of

case state is
    when ST_STATE1 =>
        a <= '1';
        b <= b;
    when ST_STATE2 => 
        a <= a;
        b <= '1';
    when ST_STATE3 =>
        a <= '0';
        b <= '0';
end case;

but if there are much more signals, and much more possible states I prefer to only list the signals that actually have to change. Will the synthesizer always generate the code equal to the second snippet?

Answer 1

To summarize the comments and to answer your 2 questions:

1. "I understand that there will be a latch for b in ST_STATE1 and a latch for a in ST_STATE2, but is this something bad?"

There is no construct as "a latch (or flipflop) for b in ST_STATE1" but as your code is inside a clocked process (as you mention in your comment) there will be a flipflop for signal b which will be set to the specified values in state ST_STATE2 and ST_STATE3 and will keep its value in state ST_STATE1. The same is true for signal a.

And there is nothing "bad" with both code snippets. I prefer the first one, but sometimes for better readability I have also used the second one.

2. "Will the synthesizer always generate the code equal to the second snippet?"

Yes, it will.