Search code examples
verilogfpgasystem-verilogvlsi

chain of shift registers

How can I implement this circuit as a chain of shift registers in verilog.

Here a and b are constants and A is a 32-bit register

A = A(t-7) + A(t-16) + a.A(t-2) + b.A(t-15) for 16<= t <= 63

Thanks

Solution

  • The implementation is the direct mapping of your formula to a shift register and some glue logic, or more formally to a finite state machine. I believe your formula is:

    for 16<= t <= 63:
A(t)  = A(t-7) + A(t-16) + a.A(t-2) + b.A(t-15)

    A is your output variable (or output function), whose current value depends on its values at t-7, t-2, and t-15. This means you need to keep its 15 previous values (for example, by using a shift register). Once you have those values, calculating your output is very straightforward.

    There are lots of samples on the web for Verilog shift register implementation. The easiest way is to describe a single register module, and then instantiate it multiple times.