I am trying to create a 16-bit adder using 2-bit adders as components (which themselves use 1-bit adder as component). However, my code doesn't compile in Quartus II. Can someone help me please? Thank you very much!
My project is consisted of 3 files: bit_adder.vhd, add2.vhd and add16.vhd. The error happens in add16.vhd:
--- bit_adder.vhd
-- description of 1 bit adder
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BIT_ADDER is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end BIT_ADDER;
architecture BHV of BIT_ADDER is
begin
sum <= (not a and not b and cin) or
(not a and b and not cin) or
(a and not b and not cin) or
(a and b and cin);
cout <= (not a and b and cin) or
(a and not b and cin) or
(a and b and not cin) or
(a and b and cin);
end BHV;
-- below is add2.vhd, a 2-bit Adder. adds two 2-bit numbers together using two 1-bit adders
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity add2 is
port( a, b : in STD_LOGIC_VECTOR(1 downto 0);
ans : out STD_LOGIC_VECTOR(1 downto 0);
cout : out STD_LOGIC );
end add2;
architecture STRUCTURE of add2 is
-- Component: two 1-bit adders
component BIT_ADDER
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end component;
signal c0, c1 : STD_LOGIC;
begin
c0 <= '0';
b_adder0: BIT_ADDER port map (a(0), b(0), c0, ans(0), c1);
b_adder1: BIT_ADDER port map (a(1), b(1), c1, ans(1), cout);
END STRUCTURE;
-- add16.vhd -- set as top level entity
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity add16 is
port (a, b : in std_logic_vector(15 downto 0);
sum1 : out std_logic_vector(15 downto 0);
cout : out std_logic_VECTOR(1 downto 0)); --_vector);
end add16;
architecture arch16 of add16 is
component BIT_ADDER
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end component;
component add2
port (a, b : in STD_LOGIC_VECTOR(1 downto 0);
ans : out STD_LOGIC_VECTOR(1 downto 0);
cout : out STD_LOGIC );
end component;
signal c0, c1, c2, c3, c4, c5, c6, c7 : std_LOGIC_VECTOR(1 downto 0);
begin
c0 <='00'; --Error (10500): VHDL syntax error at add16.vhd(26) near text "'"; expecting "(", or an identifier, or unary operator
D_adder0: add2 port map (a(0), b(0), c0, sum1(0), c1);
D_adder1: add2 port map (a(1), b(1), c0, sum1(1), c2);
D_adder2: add2 port map (a(2), b(2), c0, sum1(2), c3);
D_adder3: add2 port map (a(3), b(3), c0, sum1(3), c4);
D_adder4: add2 port map (a(4), b(4), c0, sum1(4), c5);
D_adder5: add2 port map (a(5), b(5), c0, sum1(5), c6);
D_adder6: add2 port map (a(6), b(6), c0, sum1(6), c7);
D_adder7: add2 port map (a(7), b(7), c0, sum1(7), cout);
end arch16;
1) The modules add2 and add16 must have a cin port, Why don't you add it to your design? If you want to get the correct result all the modules must have "carry in". The technique you used is Carry Ripple Adder, then in add16 each block (instance) must have a cin port that is provided from the previous block.
2) In the module add16 why the signals c1, c2, ... are 2 bits? Each block needs a cin port that is 1 bit. Also you don't need the signalc0, because in the module add16, c0 is the same cin.
3) In the module add16 why the ports of each instance (a,b,sum1) is 1 bit. It must be 2 bits.
4) In the module add16 you don't need the component BIT_ADDER. You can remove it.
I edited your code with the above changes. I simulated it and could get the correct result in Modelsim. (I didn't change the module BIT_ADDER) :
------------------------------- add2 ---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY add2 IS
PORT( a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cin : IN STD_LOGIC;
ans : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cout : OUT STD_LOGIC
);
END add2;
ARCHITECTURE STRUCTURE OF add2 IS
COMPONENT BIT_ADDER
PORT( a, b, cin : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL c1 : STD_LOGIC;
BEGIN
b_adder0: BIT_ADDER PORT MAP (a(0), b(0), cin, ans(0), c1);
b_adder1: BIT_ADDER PORT MAP (a(1), b(1), c1, ans(1), cout);
END STRUCTURE;
------------------------------- add16 ---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY add16 is
PORT ( a, b : IN std_logic_vector(15 DOWNTO 0);
cin : IN STD_LOGIC;
sum1 : OUT std_logic_vector(15 DOWNTO 0);
cout : OUT std_logic);
END add16;
ARCHITECTURE arch16 OF add16 IS
COMPONENT add2
PORT( a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cin : IN STD_LOGIC;
ans : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cout : OUT STD_LOGIC);
END COMPONENT;
SIGNAL c1, c2, c3, c4, c5, c6, c7 : std_LOGIC;
BEGIN
D_adder0: add2 PORT MAP ( a(1 DOWNTO 0) , b(1 DOWNTO 0) , cin, sum1(1 DOWNTO 0) , c1 );
D_adder1: add2 PORT MAP ( a(3 DOWNTO 2) , b(3 DOWNTO 2) , c1 , sum1(3 DOWNTO 2) , c2 );
D_adder2: add2 PORT MAP ( a(5 DOWNTO 4) , b(5 DOWNTO 4) , c2 , sum1(5 DOWNTO 4) , c3 );
D_adder3: add2 PORT MAP ( a(7 DOWNTO 6) , b(7 DOWNTO 6) , c3 , sum1(7 DOWNTO 6) , c4 );
D_adder4: add2 PORT MAP ( a(9 DOWNTO 8) , b(9 DOWNTO 8) , c4 , sum1(9 DOWNTO 8) , c5 );
D_adder5: add2 PORT MAP ( a(11 DOWNTO 10) , b(11 DOWNTO 10), c5 , sum1(11 DOWNTO 10) , c6 );
D_adder6: add2 PORT MAP ( a(13 DOWNTO 12) , b(13 DOWNTO 12), c6 , sum1(13 DOWNTO 12) , c7 );
D_adder7: add2 PORT MAP ( a(15 DOWNTO 14) , b(15 DOWNTO 14), c7 , sum1(15 DOWNTO 14) , cout);
END arch16;