VHDL when else interpretation

Question

Is it correct to have such a code where the output depends on three input signals, but the signal C is not relevant in each case? So I do not specify this C in every case.

I mean, for example, is the first case fulfilled when A and B are = 0 and then there will be X1 on Y or is this however treated as the last else and the output will be '0'.

Y <= X1 when (A = '0' and B = '0') else           
     X1 when (A = '0' and B = '1') else           
     X2 when (A = '1' and B = '1' and C = '0') else 
     X1 when (A = '1' and B = '1' and C = '1') else 
     X1 when (A = '1' and B = '0') else           
     '0';

Answer 1

Yes.

You could also rewrite it as:

Y <= X1 when (A = '0' or B = '0' or C = '1') else 
     X2 when C = '0' else             
     '0';

I would probably ignore mapping the 'X' conditions to '0' and simply write:

Y <= X1 when (A = '0' or B = '0' or C = '1') else X2 ;

if you are worried about X's in RTL you can instead do:

assert not (is_X(A) or is_X(B) or is_X(C)) report "found an X on an input" severity warning ; 

That said the point of VHDL is to write your code in its most readable form and let the synthesis tools do the reduction of the equation - if that is your first equation then leave it that way.