Edit top verilog component generated by Qsys

Question

Is it possible to modify Verilog generated by Qsys before Quartus synthesis ?

I designed a component under Qsys. I added the design.qsys file under my Quartus (14.0) project and selected it as «top-level».

Qsys generate a verilog top component named design.v but if I modify it Quartus will erase my modifications when synthesize project.

I want to modify the top component to «export» some avalon signal on fpga I/O (chipselect and write) to see it on my oscilloscope.

Answer 1

Ok, I found the solution. In fact, I selected design.qsys as «top-level». Doing this regenerate all HDL code. To avoid this, adding design.qip is a prefered way. This file can be found under the directory : design/synthesis/design.qip