Can I use concatenation, repetition, or `define with $readmemb or $readmemh?

I'm implementing a single cycle MIPS processor and initializing my memory using $readmemb or $readmemh. That being the case I want to initialize my register file with some 32-bit instructions, but I don't want to have to write those instructions out by hand.

Could I feed a scheme like the one below into $readmemh and have it initialize my memory to those values? What are my limitations with these $readmemh and $readmemb?

`define ADD 5'b0xx01
{1'b1, 5'd0, 5'd0, 5'd0, `ADD, 11'd1}
{1'b1, 5'd0, 5'd0, 5'd0, `ADD, 11'd7}

Solution

You cannot use concatenation, repetition or `define macros inside files passed to $readmemb or $readmemh. The syntax for those files is described in the IEEE Std 1800-2012, section "21.4 Loading memory array data from a file". The syntax is pretty limited. Values are separated by whitespace only, may contain optional underscores for readability, and comments are allowed (/**/ or //).

Possible alternatives include:

Use a script (such as Perl) to generate the readmem files outside of Verilog.
Use the concatenation, repetition and define syntax you've shown in Verilog in for loops.