Multiplexer on VHDL

Question

I tried to create multiplexer:

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY multiplekser IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
U : IN STD_LOGIC_VECTOR(2 downto 0);
V : IN STD_LOGIC_VECTOR(2 downto 0);
W : IN STD_LOGIC_VECTOR(2 downto 0);
X : IN STD_LOGIC_VECTOR(2 downto 0);
Y : IN STD_LOGIC_VECTOR(2 downto 0);
S : IN STD_LOGIC_VECTOR(2 downto 0);
CS : IN STD_LOGIC;
M : OUT STD_LOGIC_VECTOR(2 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END multiplekser;


--  Architecture Body

ARCHITECTURE multiplekser_architecture OF multiplekser IS


BEGIN
    PROCESS(CS)
    BEGIN
    if (CS = '1') then
        with S select
            M<=U when "000",
                V when "001",
                W when "010",
                X when "011",
                Y when others;
    else 
        M<="ZZZ";
    end if;
    END PROCESS;
END multiplekser_architecture;

but some errors has occured:

I did it on Quartus II 64 bit. Here is my block diagram:

CS is enable signal. When CS is 0, M(output) must have high impedance.

Answer 1

You're using a concurrent statement where a sequential statement is expected.

You should use a case statement or a set of if statements. For example:

architecture multiplekser_architecture of multiplekser is
begin
    process(cs, s, u, v, w, x, y)
    begin
        if cs = '1' then
            case S is
                when "000"  => m <= u;
                when "001"  => m <= v;
                when "010"  => m <= w;
                when "011"  => m <= x;
                when others => m <= y;
            end case;
        else
            m <= "ZZZ";
        end if;
    end process;
end architecture;