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verilogsystem-veriloghdl

What does [`something] some_vector ; mean in verilog?

Let's say I have some define macro, and then some other wire that is defined.
What does it mean when I have them like this? Is it just meaning to take the 2 LSBs from the wire?

`define A_DEFINE  32
// *SOME CODE IN HERE*
output  [`A_DEFINE-1:0] my_out_wire;
// *MORE CODE HERE*

I can't seem to find any explanation of this meaning.

Solution

  • The syntax `define A_DEFINE 32 declares a macro called A_DEFINE. A macro is a thing you can use for text replacement in your code.

    The syntax `A_DEFINE means expand the A_DEFINE macro. This is essentially taking the value of A_DEFINE and copying in the place where the macro is expanded.

    The preprocessor does this for you. In essence, you'll end up with:

    // *SOME CODE IN HERE*
output  [32-1:0] my_out_wire;
// *MORE CODE HERE*

    Defines are handy if you need to have a configurable element in your code. This way if you have multiple signals that are supposed to be as wide, you just use the define. In case you need to change from 32 to 64, you just modify the define and that's it.

    Also have a look at the SystemVerilog parameter. This might also be helpful.