In my book as an example it has:
wire [n-1:0] c = {1'b1,(~r[n-1:1] & c[n-1:1])};
If n=4 then c is 4 bits but the concatenation however makes 5 bits! 0.o
)r is there something I don't understand about Verilog here, that maybe the case.
The concatenation is infact just 4 bits. r[n-1:1] is an n-1 bit value which in this case is 3. Note that r[n-1:1] means the bits starting from 2nd bit (index = 1) to nth bit ( index = n-1). So a 3 bit value concatenated with 1b'1 gives a 4 bit value.