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verilogfpgahdl

Parameterized net width in Verilog

Is something like this possible ?

parameter width; wire[width-1] a_net = (width)'b0;

I basically need a variable to control the width of the right hand side. I am planning to use this in an test bench where I just have to change the parameter width at the beginning of the file, and this parameter sets the net width in all other occurrences of 'a_net'.

If this doesn't work - is there any other workaround ?

Thanks, Jim

Solution

  • I think you need to specify the LSB of your wire as well:

    parameter WIDTH = 16;

wire [WIDTH-1:0] a_net = 0;