yosys Examples and Free Source Code

ice40 clock delay, output timing analysis...

verilog fpga yosys ice40

What are PIP alternative in arachne-pnr?...

fpga yosys ice40

Understanding logic tile LC_5 bits...

yosys ice40

How to reuse BRAM once it's not needed by module?...

fpga yosys ice40

How to unpack LUTs into logic cells in verilog...

verilog yosys

Multiple conflicting drivers for reg assigned in only one always block...

verilog yosys

Sub-module not found after changing parameter through chparam in a foreach loop...

yosys

Yosys: Variable initial value to flip-flop at reset...

yosys

Is there any way to get default parameter value for verilog module with Yosys...

verilog yosys

Simplify combinational logic using yosys...

yosys

Characterization using YOSYS...

delay area energy yosys

How to remove auto-generated YOSYS comments?...

verilog yosys

iCE40 IceStorm FPGA: Switchable Pullup on Bi-directional IO pins...

yosys

Vivado doesn't recognize cell in EDIF file generated by Yosys...

yosys

Increment integer under case state in verilog with yosys...

verilog yosys

Lattice iCE40 JTAG...

fpga jtag yosys

How to output dependency files in Yosys (gcc -MMD equivalent)?...

makefile yosys

Reset behavior with miter equivalence checking...

yosys

assume() does not work for initial statement...

verilog yosys

is nested @ supported?...

verilog synthesis yosys

What is a good "template" Yosys synthesis script?...

yosys

What are yosys formal capabilities with verific?...

yosys

Yosys gives syntax error on 2d interface...

yosys

How can I use multiple IP cores that both contain modules with the same names with Yosys...

yosys

Yosys logic loop falsely detected...

yosys

Can I avoid opt_merge from removing a BUF? (Yosys tri-state workaround)...

yosys tri-state-logic

Primitives in Yosys...

verilog yosys

How to assign RAM values in an initial block in Yosys?...

verilog yosys

Understanding the bitstream generated for iCE40 I/O tiles...

yosys ice40

Is it possible to remove clock input variable from the AIGER output?...

yosys