yosys Examples and Free Source Code

Yosys/nextpnr timing report for Lattice ECP5 FPGA?...

fpga yosys icestorm nextpnr

Vivado doesn't recognize cell in EDIF file generated by Yosys...

yosys

Formal verification of state machine with SymbiYosys not giving expected results...

verilog formal-verification yosys

Yosys optimizes away ring oscillator on ice40 FPGA...

fpga yosys ice40

Verilog: mapping an memory array...

verilog system-verilog fpga yosys

In FPGA, why counter with full adder raw implementation have better clock performance than infered a...

fpga chisel yosys icestorm

Understanding the SB_IO primitive in Lattice ICE40...

verilog fpga lattice yosys ice40

Verilog/SystemVerilog: "constant" function is considered non-constant...

verilog system-verilog hdl yosys verilator

FSM export using Yosys...

verilog fsm yosys

Getting "Warning: Driver-driver conflict" errors from yosys...

verilog yosys

Yosys: Multiple edge sensitivities for asynchronous reset...

verilog signal-processing fpga yosys ice40

Support for ICE40UP5K-SG48I?...

fpga yosys icestorm

Does operator of `[]` of std::map always put the new item into the first place of iterator?...

c++stdmap yosys

How to see the synthesized RTL in openlane?...

yosys

iceprog - Can't find iCE FTDI USB device with Alchitry CU...

fpga yosys icestorm

Yosys AIG output format unclear...

yosys

Yosys -- compilation of .dot file suceeds, but viewer (xdot) can't preview it...

verilog yosys

Do sub modules get stimulated independently by the solver or through the connected top level module?...

system-verilog formal-verification yosys

Why Yosys synthesis the sequential statement to constant...

synthesis yosys

iCE40 Ultra Plus 5k — how to set PLL (without propietary GUI tools) (continued)...

vhdl fpga yosys

Yosys -- producing an electronic schematics from verilog...

graphviz dot yosys

Formal verification with yices -- broken pipe...

yosys

how to estimation a chip size with standard cell library...

yosys

Path options for techmap calls in a pass...

yosys

System Verilog Loops...

verilog system-verilog cpu-architecture hdl yosys

Adding cell to write_verilog causes error...

yosys

Error: Cannot find buffer gate in the library...

yosys

Is it possible to use $display to print some values when proving with yosys-smtbmc?...

verilog yosys

Addition/Substraction Optimization in Yosys...

synthesis yosys

Why I can not copy a content of register to another one in "always" block in Verilog?...

verilog fpga yosys iverilog