yosys Examples and Free Source Code

Extending existing cell libraries...

yosys

Superfluous buffers/inverters in synthesised netlist...

verilog synthesis yosys

Can we have variables in a Yosys script?...

yosys

Correspondence between iCE40 I/O blocks and package pins...

yosys ice40

Analyzing bitstreams using Icestorm...

yosys

Why is this MUX with const. inputs not optimised away?...

optimization verilog synthesis constant-expression yosys

How do I get multi-bit ports to work in Yosys when the module is BLIF?...

verilog yosys

Combinatorial synthesis: Better technology mapping results...

yosys

How to map clock gate to tech library cell...

verilog yosys

programming iceStorm binary file to which address?...

yosys ice40

How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?...

yosys

Computed verilog parameter in Yosys...

verilog yosys

Some questions about wires with private name in Yosys...

yosys

Why does yosys renumber vector ports?...

yosys

Conditional compilation in ice40_synth using yosys?...

command-line-interface preprocessor conditional-compilation yosys

Yosys FSM Detection State Assignments?...

verilog fsm yosys

yosys fails at ABC pass (on counter.v demo)...

synthesis yosys

iCEstick + yosys - using the Global Set/Reset (GSR)...

fpga yosys

What are the useful attributes that can be used with passes in Yosys?...

yosys

iCE40 IceStorm FPGA Flow: Bi-directional IO pins...

yosys

How to perform Depth First Search (DFS) inside a module starting from its ports?...

yosys

How to partition a top module into 2 sub-module using submod command?...

yosys

How do I get a list of unconnected cell ports using the Yosys RTLIL API?...

yosys

visualizing yosys output not working...

fpga dot yosys

Netlist validation using Yosys...

verilog yosys

Is it possible to create a simulation waveform from yosys output...

verilog simulation fpga yosys

How to simplify compound assignments in yosys...

verilog yosys

gate level parsing using yosys...

yosys

Can/does SigMap produce canonical output?...

yosys

Yosys Can't open include file...

verilog yosys