verilog Examples and Free Source Code

Preventing argument substitution in Systemverilog text replacement macro...

verilog system-verilog

Building a vector starting with 1 and followed by zeros using vector concatenation and replication...

verilog

Why does my code keep triggering the default condition in case statement?...

case verilog hdl

Define constant from expression...

verilog

HDLBits Dff8p - Reset not working when using a generate loop...

verilog hdl flip-flop

Booth encode not working, simulation included...

verilog system-verilog modelsim

What is the point of a "plain" begin-end block?...

verilog system-verilog

How to normalize the sum of two IEEE754 single precision numbers?...

floating-point verilog system-verilog ieee-754 twos-complement

XXX on output ports...

verilog hdl xilinx-ise

Writing a counter to approximate a fraction with minimal error...

verilog hdl vga

SystemVerilog FSM enum states...

verilog system-verilog register-transfer-level

Can the power operator ** be used with arbitrarily large operands?...

verilog system-verilog

How can I enable data transfer through physical contact in FPGAs?...

verilog fpga

Concatenate arrays of bytes into one array...

verilog system-verilog

Understanding the SB_IO primitive in Lattice ICE40...

verilog fpga lattice yosys ice40

Design Ones Counter Using Structural Level Modeling...

verilog counter clock bit-shift synchronous

carry look ahead adder verilog...

verilog vivado

SystemVerilog array of interfaces with unique parameters...

verilog system-verilog hdl

When designing digital circuits, which is more power efficient, an if-statement or a multiplication ...

verilog synthesis

Using right parenthesis still causes Verilog compiler to complain about expecting a right parenthesi...

verilog system-verilog

HDLBits DFFs and Gates...

verilog

Assertion in verilog...

verilog simulation assert

Analyzing synchronizer MTBF in Quartus...

verilog fpga quartus intel-fpga

Concatenate all the elements of the dynamic array with stream operator...

concatenation verilog system-verilog

Modelsim displays unknown or garbage number in transcript...

verilog simulation modelsim test-bench

Verilog/SystemVerilog: "constant" function is considered non-constant...

verilog system-verilog hdl yosys verilator

Verilog - Error: "Unresolved reference" when simulating...

verilog modelsim

The output I'm getting is wrong...

verilog system-verilog iverilog

Inferring a True Dual Port RAM (Xilinx and Intel compatible) in Verilog...

verilog fpga xilinx intel-fpga

Whether the execution order is guaranteed when the statements in fork join_any and the statements fo...

verilog system-verilog hdl