verilog Examples and Free Source Code

Debugging combinational logic loops in Icarus Verilog...

verilog iverilog

FPGA Fancy flowing light, digital tube display?...

verilog fpga vivado

Why would a simulation/synthesis mismatch occur with non-blocking initialization of signals?...

verilog vhdl system-verilog

Bitwise Reduction Operators in C...

c bit-manipulation verilog bitwise-operators bitwise-and

Unnecessary spaces in decimal display...

verilog space

How to get Vivado to properly respect recursive module instantiation?...

recursion parameter-passing verilog vivado iverilog

How do I represent large delays in Verilog?...

verilog fpga hdl test-bench

What is the difference between == and === in Verilog?...

verilog system-verilog hdl

How can I fix the errors?...

verilog

Verilog state machine state/next_state style...

verilog fpga hdl fsm

What would right value of B and C from this code?...

verilog system-verilog

Are renamed clocks synchronous?...

verilog fpga

$fopen returns the MCD, but the MCD does not work...

verilog system-verilog fopen modelsim

HDLBits edge detect question about how to update the edge state...

verilog system-verilog

Optimizing 8 to 1 mux (32 bit inputs), with shortest delay...

verilog timing

How to call tasks from a separate module in Verilog?...

task verilog iverilog

How can I fix this Verilog syntax assign error?...

verilog system-verilog

Explain this syntax error in testbench file...

verilog system-verilog test-bench

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand...

verilog quartus intel-fpga

The assignment in Verilog...

verilog variable-assignment

Verilog simulator for windows...

verilog simulation hardware simulator

How to identify synchronous resets (in verilog)...

verilog system-verilog verification

Using Module Parameter in Continuous assignment...

verilog system-verilog

I'm trying to make a UART, but the data is transferred to the z position if data is transferred ...

verilog uart

Compilation error in Quartus for Verilog language...

verilog system-verilog quartus

How to pass value to `define N...

verilog iverilog

Parallel execution of module under always block...

verilog

Helper function to define string results?...

verilog

Verilog: How to instantiate a module...

verilog system-verilog

Signal gating differences between simulators and architecture...

verilog simulation system-verilog