verilog Examples and Free Source Code

4 bit adder-subtractor in verilog...

verilog hdl iverilog

How to make an unsigned to signed number, and reverse in verilog...

verilog riscv unsigned signed

Assignment error: "Cannot assign to array"...

verilog hdl iverilog

'case item is unreachable' in Vivado synthesis process...

verilog fpga xilinx hdl vivado

Check all bits set/unset...

verilog system-verilog

Illegal assignment: Cannot assign an unpacked type to a packed type...

verilog system-verilog modelsim

Trouble instantiating and assigning in generate block...

verilog system-verilog

How to have a signal which has specific delay after clock positive edge?...

verilog test-bench

Getting unexpected output for state machine code...

verilog system-verilog state-machine

Getting wrong output for 4x4 multiplier...

verilog

Trying to design a shift adder using Verilog, and I'm not able to fix this error...

verilog iverilog

4-bit register always shows output 0...

verilog system-verilog test-bench

always_comb construct does not infer purely combinational logic...

compilation verilog system-verilog quartus

Why does this simulate continuous assignment with delay of 2 as if had delay of 3...

verilog system-verilog

Generating random value for 255 wire bus...

verilog system-verilog verification

Timing problem between posedge and negedge in a FSM...

verilog

I have a problem with the function $readmemh...

verilog system-verilog

Foreach loop with string array...

verilog system-verilog

Odd Number Detector on FPGA...

verilog fpga

Convert parity function from using unary XOR to a "for" loop...

for-loop verilog parity

Why does the Inferred Latch error occur during the synthesis process?...

verilog fpga xilinx hdl vivado

What is the nondeterminism in Verilog and simulator? Can control flow switch back and forth between ...

verilog system-verilog hdl

Vivado verilog 1 LUT cells form a combinatorial loop...

verilog hdl vivado soc

Could someone explain how the sequence of code for a 4-bit CLA adder works?...

verilog

When I simulate my counter in Modelsim, the outputs are undefined...

verilog modelsim quartus

Using a macro gives errors, but putting macro text in explicitly does work...

verilog system-verilog quartus

What happens when multiple variables in Verilog's always block's sensitive list change at th...

verilog hdl

Synopsys VCS Warning for `define redefined...

verilog synopsys-vcs

Synopsys VCS message severity change from error to warning...

verilog system-verilog synopsys-vcs

Confused about one Verilog command...

verilog system-verilog hardware