verilog Examples and Free Source Code

Rounding down the absolute value of signed fixed point numbers in Verilog...

verilog rounding fixed-point

Formal verification of state machine with SymbiYosys not giving expected results...

verilog formal-verification yosys

Matrix Multiplication Testbench Yields Inconsistent Results...

verilog system-verilog test-bench iverilog

Verilog Barrel Shifter...

rotation verilog bit-shift shift case-statement

Design with MicroBlaze has more instantiated block-RAMs than device capacity. Consider targetting to...

verilog vivado

IO placement is infeasible error in Vivado...

constraints verilog fpga vivado

No .vcd file found error, but I have used the $dump code...

verilog system-verilog test-bench iverilog edaplayground

How to include time delay in synthesized verilog?...

verilog timedelay

Verilog module always going to default case when assigning value to input...

verilog fpga quartus intel-fpga questasim

Quartus-FPGA: Disable Path Optimization...

verilog fpga quartus intel-fpga

Store constants in a file, use for module Instantiation in generate block...

constants verilog system-verilog

Module instantiation when number of ports are dynamic...

module verilog generate

Question about the behaviour of registers...

verilog cpu-architecture system-verilog

Issue with Buffers for Input Feature Maps and Neural Network Weights...

verilog

array of buffers in verilog...

verilog system-verilog

Output comes 1 clock cycle later than expected...

verilog register-transfer-level

How to initialize coefficients of a large digital filter in Verilog?...

verilog signal-processing fpga vivado digital-design

Determine if a module in SystemVerilog is synthesizable...

conv-neural-network verilog system-verilog fpga max-pooling

Verilog: mapping an memory array...

verilog system-verilog fpga yosys

Can anyone help me to create a Verilog testbench?...

input verilog system-verilog test-bench

output of the word on the 7 segment indicator by using switch...

verilog system-verilog test-bench

calculation of simulation time in verilog...

verilog simulation

Checking for amount of open files while running SystemVerilog testbench...

verilog simulation system-verilog test-bench synopsys-vcs

Module that converts ASCII to 7-segment display using FPGA...

verilog system-verilog fpga

Timing closure problems in FIFO...

verilog timing xilinx fifo vivado

icarus verilog: Unable to bind variable...

verilog system-verilog iverilog

Error: "Syntax in assignment statement l-value." while trying to assign a reg inside an al...

verilog iverilog

How to define and initialize a vector containing only ones in Verilog?...

verilog system-verilog register-transfer-level

Simulation contradiction using the same Vivado block ram IP...

verilog simulation ram vivado test-bench

Verilog testbench code using gEDA and iVerilog...

verilog hdl iverilog