hdl Examples and Free Source Code

Can't printf with PeekPokeTester in Chisel3...

scala sbt hdl chisel

Verilog: proper way of connecting ports...

verilog hdl

Is there a way to warn wrong clock domain crossing in Chisel3?...

hdl chisel

ModelSim compile successfully but i have wrong declaration in my code...

verilog hdl modelsim

Question about triggering of always blocks...

verilog system-verilog execution hdl

Concurrent signal assignment with vector in VHDL...

concurrency vhdl hdl ghdl

Verilog - take in input from multiple "sensors", increment "count"...

verilog fpga hdl

Verilog HDL error: Illegal left-hand side assignment...

verilog hdl

Why is computing two's compliment in a single Verilog statement (i.e. ~x + 1'b1) producing t...

verilog system-verilog hdl

What's a good way to "fuse" the locations pointed to by different pointers?...

perl pointers memory reference hdl

Input Port Declaration with two sizes...

system-verilog hdl

How to define a custom cell for netlist synthesis?...

embedded hdl synthesis netlist

Why always block not reactivating when there is a reassignment of logic described in sensitivity lis...

verilog system-verilog hdl synopsys-vcs

Verilog Testbench Clock...

verilog hdl

Variable slicing vector Systemverilog...

verilog system-verilog hdl

Learn VHDL when coming from strong Verilog background...

vhdl verilog hdl

Difference between D Latch Schematic and D Flip Flop Schematic...

computer-science hardware hdl flip-flop circuit-diagram

Valid-Ready handshake in Verilog...

verilog system-verilog hdl

Verilog/SV conditional variable definition...

verilog system-verilog hdl

AHDL dff resets to it default value...

hdl intel-fpga

How to use experimental features in Chisel3?...

scala hdl chisel

Error with localparam inside "for" loop on Verilog...

verilog hdl

I have error in `define on the Verilog with for...

verilog hdl

Why verilog "always_comb block contains only one event control" error flagged on always pr...

verilog system-verilog hdl

How to access Verilog genvar generated instances and their signals...

verilog system-verilog hdl xilinx-ise

checking next condition in the if statement when whole condition will be true...

vhdl standards hdl

verilog synthesis not converging after 2000 iterations...

verilog hardware xilinx hdl

How to ensure a signal is high until another signal has been asserted in System Verilog...

verilog system-verilog hdl system-verilog-assertions

What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)...

verilog vhdl hdl

What the difference between <= and = in cocotb?...

hdl cocotb