hdl Examples and Free Source Code

Parameterizing a module based on an interface (SystemVerilog)...

verilog system-verilog hdl

Is there a way to guard the creation of covergroup bins...

verilog code-coverage system-verilog hdl test-bench

Verilog execution parallel or sequential if block along with another statement...

verilog fpga hdl sequential

Why this chisel code compiling without error with wrong size UInt assignement?...

hdl chisel

How to connect a Flow to a Stream in SpinalHDL...

hdl spinalhdl

Why are instantiated modules often given the net name "u"?...

verilog naming-conventions terminology hdl

Can't poke MixedVec...

scala hdl chisel

What is the purpose of 'pure' keyword in the clash tutorial example?...

haskell hdl clash

Vec of Bundle as a Module parameter...

scala hdl chisel

Can a function in verilog call another function?...

function verilog system-verilog hdl register-transfer-level

Color to grayscale conversion...

c++opencv grayscale hdl

== operator in assign statement (Verilog)...

verilog system-verilog ternary-operator assign hdl

How to use parameterized bitwidth for a constant value in Verilog?...

verilog system-verilog hdl digital-logic register-transfer-level

How to pass some Bundles as Module parameters?...

scala hdl chisel

Expression _GEN_7 is used as a FEMALE but can only be used as a MALE...

scala hdl chisel register-transfer-level

How to do parallel testing with peekpoketester in chisel3?...

scala coroutine hdl chisel

What is the difference between $signed and signed' in verilog?...

logic verilog system-verilog hdl register-transfer-level

How to count time in chisel with iotesters?...

hdl chisel

RisingEdge example doesn't work for module input signal in Chisel3...

hdl chisel icarus cocotb

Is RawModule only for Top connections?...

hdl chisel

Is it possible to pass constant parameters UPWARDS through module hierarchy in Verilog / SystemVeril...

parameters verilog constants hardware hdl

How can I get the index of a one-hot encoded vector without using a for-loop?...

vhdl hdl

ALU hdl produces wrong values...

hdl alu

nand2tetris. Memory implementation...

memory hdl nand2tetris

Is there a way to monitor the state of an internal signal with a University Program VWF in Quartus 1...

vhdl fpga hdl quartus

First assign and then reassign in if block as alternative to if-(else if)-else in Verilog...

logic verilog hardware hdl

i have some problem about current time in vhdl...

vhdl fpga hdl

Efficiently implementing DXT1 texture decompression in hardware...

gpu vhdl texture-mapping hdl dxt

Can a sequential always block be triggered by a short pulse from a combi block...

verilog compiler-optimization system-verilog hdl

How do I set output flags for ALU in "Nand to Tetris" course?...

hdl alu nand2tetris