hdl Examples and Free Source Code

array bit parameter range in verilog - underflow or -1...

verilog fpga system-verilog hdl modelsim

VHDL Two Type Declarations In A Package Create An Error...

vhdl hdl vivado

How can I see why a file is listed in "syntax error files" in vivado...

syntax-error hdl vivado

Verilog error in modelsim- near "=": syntax error, unexpected '=', expecting IDENT...

verilog simulation hdl modelsim

Specman soft select on variable, decimal vs. hexadecimal values...

verification hdl specman e

CRC-32 algorithm from HDL to software...

matlab fpga crc hdl crc32

System Verilog subtraction removing important bits...

verilog system-verilog xilinx hdl vivado

Can clock edge events be synthesized inside always blocks in verilog?...

events verilog hdl synthesis

Giving inputs to error checking module from PRBS generator in verilog...

verilog fpga hdl

HDL counter and flag coding style...

verilog hdl digital-logic

Specman/e list of lists (multidimensional array)...

aop verification hdl specman e

Is it possible to write verification procedures on simulations in ModelSim?...

vhdl hdl modelsim

BCD Adder in Verilog...

sum verilog hdl bcd

Chisel, Generate Blocks and Large Intermediate/Output Files...

hdl chisel loop-unrolling

Interface from DE1 board to PC in VHDL...

vhdl fpga uart hdl intel-fpga

Verilog: Assigning a localparam to a bit vector wire...

verilog hdl

Behaviour of Blocking Assignments inside Tasks called from within always_ff blocks...

verilog system-verilog hdl

Why cant my verilog testbench display intermediate variables?...

verilog system-verilog hdl test-bench

Outputs of verilog testbench are all x or z...

verilog hdl test-bench

Verilog case statement returning incorrect values...

verilog fpga hdl case-statement

Array aggregation on self-defined types?...

vhdl hdl vivado

Prevent systemverilog compilation if certain macro isn't set...

macros compilation verilog system-verilog hdl

Parameterized function errors...

verilog system-verilog hdl modelsim

Found 'module' keyword inside a module before the 'endmodule'...

verilog system-verilog hdl

Verilog - Why I can't declare multiple vars in a for statement?...

for-loop verilog hdl

Rewrite long xor statement...

system-verilog hdl

Compiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation...

hardware system-verilog hdl

Reduction operator does not work properly...

verilog counter system-verilog hdl fsm

What is a LINT/synthesis safe statement to throw an error at compile time?...

verilog hdl

Verilog: How to assign the an inout to another inout?...

verilog fpga hdl