hdl Examples and Free Source Code

chip Mux4way16 not run ontil the end on ‏HardwareSimulator (VHDL)...

hdl nand2tetris

Verilog always block with no sensitivity list...

verilog system-verilog hdl

Data is not picked up from instantiated outputs...

hardware verilog fpga hdl

Verilog: Mix of blocking and non-blocking assignments to variable <inc_data_int> is not a reco...

verilog hdl

Verilog Vending machine FSM...

verilog fpga hdl

Verilog, Parallel in Series out Shift Register...

verilog hdl shift-register

System Verilog Loops...

verilog system-verilog cpu-architecture hdl yosys

Using case statement and if-else at the same time?...

verilog hdl

Null item error when placing factory registration within a function...

system-verilog verification hdl uvm

Is it possible to declare conditionnal signals in io bundle?...

scala hdl chisel

NAND gate not working properly in this HDL?...

hdl nand2tetris

ALU test bench using test vector file not working...

verilog hdl modelsim test-bench alu

Verilog Synthesis Error (Synth 8-151): Case item is unreachable...

switch-statement conditional-statements verilog hdl unreachable-code

How to write this for loop conditions in Verilog design correctly?...

verilog hdl

Error: ordered port connections cannot be mixed with named port connections...

verilog hdl

How to write a behavioral level code for 2to4 decoder in verilog?...

verilog hdl test-bench

If statement and assigning wires in Verilog...

logic hardware verilog hdl

Parameter array in Verilog...

verilog hdl

Verilog: More efficient way to use ternary operator...

conditional-statements verilog assign conditional-operator hdl

How to set a signal at both posedge and negedge of a clock?...

verilog hdl xilinx-ise

Is there a synthesizeable task or port interface way to better assign AXI signals to local modules?...

verilog system-verilog hdl

Verliog- comparator...

compare verilog hdl

Systemverilog recursion update value for next stage...

verilog system-verilog hdl

Blocking assignments in always block verilog?...

verilog hdl

What happens if you add a default case to a full case statements?...

verilog system-verilog hdl

How to specify sample delay in SystemVerilog covergroup...

verilog system-verilog hdl system-verilog-assertions register-transfer-level

Verilog testbench outputs are x and z on a 16-bit carry adder...

logic verilog hdl iverilog

VHDL to Verilog...

vhdl verilog system-verilog hdl

Setting registers using a one-hot signal...

verilog hdl

How to define output Reg in Chisel properly...

hdl chisel register-transfer-level