hdl Examples and Free Source Code

Verilog/SystemVerilog: "constant" function is considered non-constant...

verilog system-verilog hdl yosys verilator

Whether the execution order is guaranteed when the statements in fork join_any and the statements fo...

verilog system-verilog hdl

4 bit adder-subtractor in verilog...

verilog hdl iverilog

Assignment error: "Cannot assign to array"...

verilog hdl iverilog

'case item is unreachable' in Vivado synthesis process...

verilog fpga xilinx hdl vivado

Using Chisel Submodule within another Module: Cannot assign variables to the io input...

scala hdl chisel

if-else condition for custom libraries in VHDL...

vhdl fpga hdl vivado

VHDL when running ghdl -r my testbench is getting stuck after passing two values...

vhdl hdl test-bench alu ghdl

Why does the Inferred Latch error occur during the synthesis process?...

verilog fpga xilinx hdl vivado

What is the nondeterminism in Verilog and simulator? Can control flow switch back and forth between ...

verilog system-verilog hdl

Vivado verilog 1 LUT cells form a combinatorial loop...

verilog hdl vivado soc

Difference between combinatoric signal dependant on clocked signal vs. registering it...

fpga hdl

What happens when multiple variables in Verilog's always block's sensitive list change at th...

verilog hdl

Syntax error when implementing a Mux gate in Nand2Tetris...

hardware hdl nand2tetris

Synchronizing Negative-Edge and Positive-Edge Triggered Flip-Flops in HDL...

verilog system-verilog hdl

Illegal reference to net data in my inout datatype...

verilog hdl

Code to generate a periodic waveform always shows output as 0...

verilog hdl

What happens if I dont specify the size and base format for unknown state?...

verilog system-verilog hdl

What is "first node name can be top of a hierarchy in Verilog" mean?...

verilog system-verilog hdl

Verilog Latch in always@(posedge clk)...

verilog hdl

Check if a signal is active for 100 clock ticks?...

verilog hdl

Need help in converting verilog module without input & output ports into synthesizable. Because ...

image verilog system-verilog xilinx hdl

Iterating over struct members, SystemVerilog...

verilog system-verilog hdl register-transfer-level

Why am I getting parse error in reg declaration?...

compiler-errors verilog hdl icarus

Unable to compile Micron's DDR3 memory model in Modelsim...

verilog fpga hdl modelsim

Why would a non-blocking assignment like this cause the process to re-enter？...

verilog simulation hdl

Cannot find why value doesn't jump to expectation in the right time...

verilog system-verilog hdl

Verify Parameters in Verilog...

verilog hdl xilinx-ise

Verilog execution order...

verilog hdl

Count number of ones in array...

verilog system-verilog hdl