hdl Examples and Free Source Code

Multiplying number by ten in verilog...

verilog hdl

In Verilog, counting and outputting the number of 1's in an 8bit input?...

verilog hdl 8-bit

How to get size of UInt() in chisel?...

hdl chisel

Verilog gate definition difference...

logic verilog hdl

How to multiply matrices containing floating points in FPGA?...

matrix floating-point verilog simulink hdl

What is a difference between following two logic implementation from Hardware perspective?...

system-verilog hdl

DMux.hdl failure when in=1, sel=0...

debugging hdl hardware nand2tetris

Trying to build a PC (counter) for the nand2tetris book, but I'm having some trouble with the lo...

assembly hdl nand2tetris

Verilog module in Xilinx "signal never used" error...

verilog xilinx hdl

Vivado Sim Error: "root scope declaration is not allowed in verilog 95/2K mode"...

verilog xilinx hdl vivado

AXI4 delay transactions...

vhdl hdl vlsi axi4

What is difference between index(9) and index(9 downto 9) in vhdl?...

vhdl hdl vlsi

Maximum bit-width to store a summation of M n-bit binary numbers...

verilog hardware fpga hdl

Testing workflow for small (i.e. one person) design in SystemVerilog...

unit-testing fpga system-verilog hdl uvm

Making Vivado Synthesis "A process triggered every clock cycle will not have functionality ever...

verilog hdl synthesis vivado

How do you get a parameter of unknown width?...

verilog hdl

Finite state machine VHDL reset...

vhdl hdl state-machine quartus

Initialize data in Mem (Chisel)...

scala memory fpga hdl chisel

Multiplication with Fixed point representation in VHDL...

vhdl multiplication hdl fixed-point

What's the minimum clock cycles number to read and write with AXI4Lite...

arm xilinx hdl bus amba

If there are 2 always blocks which block will be executed first...

verilog system-verilog hdl

Entity Instantiation Inside of a Process...

vhdl hdl xilinx-ise digital-logic

Implementing a 4 bit counter using D flipflop.in Verilog...

verilog counter fpga hdl

RANDOM 0, 1, -1 IN VERILOG...

verilog fpga hdl

Verilog FSM and module instantiation...

verilog hdl state-machine

How can write code in verilog shorter using case sentence...

verilog fpga system-verilog hdl

SystemVerilog Instantiated Modules Share Inputs When They Shouldn't (Easy Solution)?...

module counter instantiation system-verilog hdl

"unexpected others" in vhdl...

vhdl xilinx hdl

Formatting Excel Cells for Binary...

excel excel-formula hdl

iverilog syntax for include?...

verilog hdl iverilog