hdl Examples and Free Source Code

"unexpected others" in vhdl...

vhdl xilinx hdl

Formatting Excel Cells for Binary...

excel excel-formula hdl

iverilog syntax for include?...

verilog hdl iverilog

Synthesis global instance count...

vhdl verilog hdl synthesis

Initialize array of integer...

vhdl hdl

What does "quality of result (QoR)" cover?...

vhdl verilog fpga hdl asic

Error (10170): expecting "<=", or "=", or "+=", or "-=", ...

syntax-error verilog hdl intel-fpga accumulator

swap two variables in verilog using XOR...

verilog fpga xor hdl

How to change input signal to parameter in systemverilog?...

verilog fpga system-verilog hdl

Reassign a variable multiple times within a clock cycle - Chisel...

scala loops hdl chisel

SystemVerilog: Assignment pattern element <name>: Element widths don't match (error: vlog-...

arrays fpga system-verilog hdl

How to change the code. 16bit CLA (carry-look.ahead adder) verilog code simulation...

verilog hdl

Use generic type to turn off logic in datapath (Chisel)...

scala generic-programming hdl riscv chisel

verilog, why is this illegal reference to net...

verilog hdl digital digital-logic

What does '&' and '%' mean in operators -&, -%, +&, +% in Chisel3?...

scala hdl chisel

8bit adder not working properly...

verilog hdl

Is event trigger synthesizable in verilog?...

verilog hdl synthesis

Bit vector comparison in Chisel...

arrays scala vector hdl chisel

Simple verilog to control MD1715 ultrasound driver...

verilog hardware fpga hdl

Can we use ternary operator inside an always block? Is MOD(%) operator synthesizable?...

verilog hdl synthesis vivado

How to initialize a class type used as a function parameter...

c++ubuntu visual-c++hdl verilator

Displaying a bus in Verilog...

verilog hdl

Using 'assign' for binding module ports...

verilog hdl

Verilog HDL behavioral coding calling modules for ALU...

overflow verilog hdl alu

Vivado 2016.2 Simulator doesn't support System Verilog $cast or $sformatf...

verilog system-verilog hdl vivado test-bench

How to choose one of top architectures in VHDL (from one file)?...

vhdl hdl

Syntax error near end in Verilog...

verilog hdl

Verilog, generate/loop with parameterized array declaration...

arrays verilog system-verilog hdl

Bitshifting std_logic_vector while keep precision and conversion to signed...

bit-manipulation vhdl fpga bit-shift hdl

Verilog/SystemVerilog inferred latch in case statement...

arrays switch-statement verilog system-verilog hdl