Why doesn't the DspContext work such as withNumAddPipes?...

How to writing a accumulator by using ScalaBlackBox?...

firrtl.Driver is deprecated - but what should we use instead?...

How to duplicate a single bit to a UInt in Chisel 3?...

What is the purpose of the makeSink method in making IOs for a periphery...

declaration and Variable scope in chisel and When block...

Can't printf with PeekPokeTester in Chisel3...

Why multiple HCL languages...

Is there a way to warn wrong clock domain crossing in Chisel3?...

How to use a chisel3.experimental.ChiselEnum in an I/O port?...

How to generate an [error] instead of an [info] upon seeing a wrong value in expect()...

Chisel3: How to create a register without reset signal in RawModule?...

What mechanism works to show component ID in chisel3 elaboration...

Not sign-extended in AND operation in firrtl...

Type Class for Complex Numbers...

Why does implicit type conversion from Int to UInt not work?...

Conditional Bulk Connection <>...

How to get the PeekPokeTester expect function to print signal values in hex?...

How to printf or println UInt in chisel?...

Compiling Modules Separately and Linking...

How to iterate through similar registers definition in Chisel (regmap)...

Testing a DSPComplex ROM...

How to use experimental features in Chisel3?...

Building a DspComplex ROM in Chisel...

Chisel testbenches: controlling multiple ports independently...

How to generate Verilog code with parametized modules in Chisel?...

How to decipher comments in generated Verilog from chisel?...

How to make assertions in Chisel be just warnings and not stop simulation...

what is "wxd" in rocketcore?...

Firrtl runs of out of heap memory with large input...