chisel Examples and Free Source Code

How to config xLen in rocket core?...

riscv chisel rocket-chip

ListLookUp in CHISEL...

scala riscv chisel

The type mismatch error while using Chisel3 BlackBox...

riscv chisel

Assigning values to the elements of a bundle by parsing a file...

scala chisel

Vector of RegEnable...

chisel

How to delete clock signal on chisel3 top module?...

verilog xilinx chisel

Implement a Verilog $onehot task in Chisel...

scala one-hot-encoding chisel

assigning a signal to a non parent module...

chisel

Firrtl parser syntax errors for custom Record type...

scala chisel

How to init a register with a parametrized value...

scala chisel

What is the difference between using UInt, SInt Bits types in Chisel?...

chisel

How to use chisel dsptools with floats...

scala fixed-point chisel

Chisel: Decoupled directionality lost in nested Vecs...

chisel

Advanced Parameterization Manual in Chisel...

chisel

How to add reset to the Queue chisel class...

chisel

How to add a sbus master to rocket-chip periphery...

chisel rocket-chip

What is the <> operator in Chisel?...

scala chisel

How to avoid multiple design elaborations in Chisel testers...

chisel

Error after running "sbt test" in Chisel 3...

scala chisel

test rocket chip util 'Arbiters.scala', got error 'bits operated ... must be hardware .....

chisel

Sink and Source are different length Vecs...

concatenation chisel

Required: T Chisel Error...

chisel

Rocket chip simulation shows unexpected instruction count...

riscv chisel verilator rocket-chip

How to give unique name to every element in a Seq of Modules in the final Verilog file...

chisel

Implement high impedance 'Z' input output property with chisel...

fpga chisel spartan

Wiring Seq of chisel modules...

chisel

How to create array of the module? Use Array or Vec?...

scala chisel

Under Chisel 3, it takes 10 min to compile the Verilator generated C++ of Rocket Chip. Are there any...

riscv chisel

How to specify chisel’s post-processor?...

chisel

How to add additional IO under certain condition to RoCCIO in Chisel...

riscv chisel