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verilogsystem-verilogxilinx

Printing signed integer value stored in a variable of type reg


How do I print a signed integer value stored in an 8-bit register declared as:

reg [7:0] acc;

Using:

$display("acc : %d", acc)

It prints the unsigned value.

What's the correct syntax for the $display function?


Solution

  • If you declare the reg as signed, $display will show the minus sign:

    module tb;
    
    reg signed [7:0] acc;
    
    initial begin
        acc = 8'hf0;
        $display("acc : %d", acc);
    end
    
    endmodule
    

    Prints out:

    acc :         -16