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stringasciiverilogsystem-verilog

Assign ASCII character to wire in Verilog

I understand that you can declare a string in a Verilog test bench as follows:

reg [8*14:1] string_value;  

initial 
    string_value = "Hello, World!";

I can then do things with this string, like use $display in a test bench to display it.

I haven't been successful in doing the same in a module when I flash it to my FPGA: 

reg [8*14:1] string_value;  

always @(reset) 
begin
    string_value = "Hello, World!";
    // Do stuff with string value

Even assigning a single value does not work:

reg [8:1] char_value;  

always @(reset) 
begin
    char_value = "A";
    if (char_value == 8'h41)
        // Do stuff!

I want to shift the individual characters on an 8-bit bus to an LCD screen for display.

How can I work with strings in Verilog?

Solution

  • SystemVerilog should support string assignment as mentioned in spec:

    For example, to store the 12-character string "Hello world\n" requires a variable 8x12, or 96 bits wide. 
     bit [8*12:1] stringvar = "Hello world\n";

    Not sure if the old verilog supports it or not.