If I have a N bit coverpoint, and I want to generate N bins, each bin corresponding to 1 bit of my coverpoint such that each bin covers 0->1 transition for each bit of the signal, how do I proceed? I know I can say bins[] = {8'b00000000 => 8'b11111111} and another way is to define coverpoint for 1 bit and instantiate it 8 times for a 8 bit coverpoint signal, but that's not what I want. It is a functional coverage and a separate bin is required for covering each line of the signal, that it is asserted. It can be addressed with toggle coverage(yes) but I need to do a functional coverage here.
I have intrpt defined as logic [63:0] intrpt deep in the design. And then a snippet of my coverage class looks like below
covergroup xyz;
option.per_instance = 1;
option.get_inst_coverage = 1;
coverpoint top.abc.intrpt {
bins asserted[] = {0=>1};
}
The idea here is to have a coverage for each input interrupt line like
bin[0] hit corresponds to intrpt[0] was asserted
bin[1] hit corresponds to intrpt[1] was asserted
......
bin[63] hit corresponds to intrpt[63] was asserted
There are many ways of collecting functional coverage; a covergroup in SystemVerilog is just one of several constructs. A executable testplan will let you link a requirement to a
You'll need to check your tools documentation on how to create the linkage.
If you are intent on using an array of covergroups, you can connect each bit of a vector to a covergroup element.
covergroup xyz(int index) @(posedge clk);
option.per_instance = 1;
coverpoint top.aintrpt[index] {
bins asserted = {0=>1};
}
endgroup
xyz cg[N];
initial foreach(cg[i]) cg[i] = new(i);