SystemVerilog FSM enum states

Question

I'm trying to implement the following state diagram in SV:

With these output logic:

With the following code:

`timescale 1ns / 1ps

 module fsm_example2(input logic clk,
                input logic reset,
                input logic TA,TB,
                output logic [1:0]LA,LB);
         
typedef enum logic [2:0] {S0, S1, S2, S3} statetype;
statetype state, nextstate;     

// state register
always_ff @(posedge clk, posedge reset)
    if (reset) state <= S0;
    else state <= nextstate;            
    
// next state logic
always_comb 
    case (state)
        S0: if(TA) nextstate = S0;
        else nextstate = S1;
        S1: if(TB) nextstate = S0;
        else nextstate = S1;
        default: nextstate = S0;

    endcase

// output logic
assign LA[0] = ~S1 | S0;
assign LA[1] = S1;
assign LB[0] = S1 | S0;
assign LB[1] = ~S1;
endmodule

But the RTL schematic doesnt appear to have the right circuitry.

My guess is on the typedef enum definition on the states.

Answer 1

A couple of problems. S0-S3 are constants, so LA and LB are being assigned constant expressions.

Also, your output expressions are 2-bits, yet you are assigning them to 1-bit wires.

You probably need something like this:

assign LA[1] = state==S1;

You should be able to figure out the other assignments.