Using right parenthesis still causes Verilog compiler to complain about expecting a right parenthesis (')')

Question

I'm getting this compile error (I changed names to arbitrary names, and inserted dots to make the error position mark '|' point to the error location on the screen here. The error position points to the last closing parenthesis mark):

file:
../../chip1dsn/chip1x_abxclst/ababx_cluster/chip1x_aabx_cluster.sv  
`AABX_PG_TEMPLATE_CHIP1M(0);                        
.................................................................|

xmvlog: *E,EXPRPA
(../../chip1dsn/chip1x_abxclst/ababx_cluster/chip1x_aabx_cluster.sv,802|27):
expecting a right parenthesis

This comes from the below line, which is a macro for a component instantiation:

`AABX_PG_TEMPLATE_CHIP1M(0);

The macro AABX_PG_TEMPLATE_CHIP1M is defined like below in an include file:

`define AABX_PG_TEMPLATE_CHIP1M(num) \
CHIP1X_AXEMIS_PG                                                                             \
#( USE_XEC_CHIP1 = 0 )                                                                       \
u20_aabx_pg``num (                                                                        \
    .AABX_ID                          (16'h``num                              ),          \
 ... (continued) ...

I can't figure out why it's giving me this compile error. I just added the parameter overwrite line #( USE_XEC_CHIP1 = 0 ) between module name and the instance name.

The macro's parameter is used to make the instance name, I put a right parenthesis when calling the macro, but it is complaining that I missed the right parenthesis.

What is wrong?

Answer 1

There's too much code missing to be certain, but from what's present I'd say:

1. a backslash is required at the end of every define-macro line (except the last)
2. Module instantiations DO NOT assign parameter value with equal sign (=) notation. Provide values via "ordered" or "named" assignment (latter preferred).
3. Remove the final comma from your port list connections