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concatenationverilogsystem-verilog

Concatenate all the elements of the dynamic array with stream operator

I want to concatenate all the elements of a dynamic array and left shift the entire array by say 8-bits. I tried the below code, and it works. Is there a better way to shift entire array without packing with streaming operator and then shifting?

module tb();
    bit [31:0] payload[3];
    bit [32*payload.size()-1:0] stream;
    bit [(32*payload.size()+8)-1:0] shifted_stream;  

    initial begin
        payload[0]='habcdabcd;
        payload[1]='hefefefef;
        payload[2]='h12345678;
        stream={<<32{payload}};
        $display("stream=0x%h", stream);
        shifted_stream = {stream, 8'h0};
        $display("shifted stream=0x%h", shifted_stream);    
     end
endmodule
Solution

  • You can do

    stream = {<<512{payload}};

    or

    foreach(payload[i])
  stream[i*512+:512] = payload[i];