Variable sized type in Chisel

Question

I have the following code that compiles:

class S extends Bundle { 
  val channels = VecInit.fill(7)(UInt(32.W))
}
class D extends Module {
  val v = IO(Flipped(Decoupled(new S)))
  v.ready := true.B
}

But running a simulation gives the error:

[error] chisel3.package$ExpectedHardwareException: vec element 'UInt<32>' must be hardware, not a bare Chisel type. Perhaps you forgot to wrap it in Wire() or IO()?

Changing the code to

 val channels = VecInit.fill(7)(Wire(UInt(32.W)))

or

 val channels = VecInit.fill(7)(IO(UInt(32.W)))

gives the following error:

[error] chisel3.package$ExpectedChiselTypeException: Bundle: S contains hardware fields: channels: D.v_channels: Wire[UInt<32>[7]]

How can I define a custom type in Chisel with a (compile time) variable number of channels?

I just want a variable size custom type that compiles and runs.

Answer 1

I reproduced the error on Scatie here.

  val channels = VecInit.fill(7)(UInt(32.W))

It's not the right way to declare UInt() vector. You should declare it like describe in cookbook:

  val channels = Vec(7, UInt(32.W))

It works in scatie.